Over the years, various standards have been applied to permit connection of peripheral devices (i.e., peripheral expansion boards) to a computer mainboard. Parallel bus standards, such as Industry Standard Architecture (“ISA”), Extended ISA (“EISA”), Micro Channel Architecture (“MCA”), Video Electronics Standards Association Local Bus (“VLB”), Accelerated Graphics Port (“AGP”), and Peripheral Component Interconnect (“PCI”) specified the computer expansion buses predominately used at various times in the recent past.
As computing speeds and input/output requirements increased, the disadvantages of parallel buses became apparent. The large number of conductors and the space required by the conductors make parallel buses costly. The transfer rate of parallel buses is limited by the skew (the delay differences) of the different signal paths.
To overcome these, and other, problems presented by parallel bus solutions, the computer industry has developed and implemented serial interconnect standards. The fewer conductors used by serial interconnect schemes lowers system cost by reducing board, cable, and connector size. By reducing the number of signal paths, serial interfaces allow for an increase in transmission rates that compensate for the reduced width of the serial data path.
Peripheral Component Interconnect Express (“PCI Express” or “PCIe”) is a serial interconnect standard designed to replace various parallel bus standards (e.g., PCI, AGP, etc.) in computer systems. PCIe provides a point-to-point topology wherein each device can have a dedicated connection to each other device through a crossbar switch. A dedicated connection between two devices is termed a link. A link is composed of up to 32 lanes. A lane is a full-duplex communication path made up of two differential pairs, each differential pair carrying data in one direction.
The first generation PCIe specification (“PCIe 1.X”) provides for data transfers at 2.5 giga-bits per second (“Gb/s”) per lane. The second generation PCIe specification (“PCIe 2.X”) provides for double the rate of the first generation specification, i.e., 5 Gb/s per lane. Aggregating multiple lanes in a link increases the available data rate in accordance with the number of lanes. While PCIe 2.0 maintains backward compatibility with PCIe 1.0, allowing use of PCIe 1.0 devices in a PCIe 2.0 system, the difference in data rates employed under the two specifications creates a variety issues. Methods of improving the level of compatibility between different PCIe generations is desirable.